The number of transistors in digital integrated circuits including but not limited to central processing units (CPUs), graphics processing units (GPUs), memory (for example, double data rate (DDR) and similar) and application-specific integrated circuits (ASICs) generally increases from one generation to the next, driven by market demand for faster and smaller processing capability. This trend has an impact on the point of load (POL) direct current to direct current (DC/DC) converters that convert a system DC voltage to an integrated circuit “core” voltage. Specifically, incremental density improvements in digital integrated circuits tend to cause incremental reductions in typical core voltage ranges and corresponding increases in core load currents. Many commonly used DC/DC topologies used in POL applications use some form of a switched-inductor switch mode power supply (SMPS), with one example being a synchronous buck DC/DC converter. In this example, the synchronous buck DC/DC converter output voltage is set by controlling its duty cycle for a given input voltage. Ideally, if, for example, an output voltage of 1.2V is required, and an input of 12V is provided, then an ideal buck regulator ON-time divided by the switching period (TON/T) would nominally be equal a duty cycle (D) of about 10%. The input voltage multiplied by the duty cycle would nominally yield the output voltage desired. In closed loop operation with lossy components employed, the actual duty cycle will be greater than the nominal duty cycle described.
It is often advantageous to interleave multiple switched inductor ‘phases’ each designed to support a fraction of the full processor current as opposed to having one ‘large’ phase designed for supporting all the processor current. The benefits of interleaving multiple phases are well established. A partial list of the system benefits of switched-inductor multiphase interleaving are efficiency improvements when employing phase adding/dropping proportional to the load current, reduction in voltage ripple at the DC/DC converter output, and the opportunity for improved transient response.
Multiphase interleaving requires circuitry to position switched inductor ON-times evenly over time if operating in a steady-state condition. For example, in a two-phase synchronous buck converter running in steady-state conditions with a switching frequency of 1 MHz (therefore a switching period ‘T’ of 1.0 μs per phase), it is desirable to delay the turn-ON of phase 2 relative to phase 1 turn-ON by ‘T’ divided by two, or 500 nanoseconds (ns). When expressing this phase relationship in terms of phase angle, phase 2 would be 180 degrees out of phase with respect to phase 1 for typical 2-phase sync-buck interleaving in steady state operation. To generalize the desired multiphase interleaving behavior in terms of phase angle in units of degrees, for ‘N’ number of active phases, the phase angle (expressed in degrees) from one active phase to the next active phase becomes (360°)/N. There are a number of proven multiphase interleaving algorithms implemented in existing DC/DC ‘controllers’ that yield multiphase interleaving. Some approaches require a fixed switching frequency, yielding a form of classical multiphase pulse-width modulation (PWM). Some other approaches that yield multiphase interleaving support the interleaving of constant ON-times, with OFF times allowed to vary, resulting in switching frequencies that are not held constant. There are many existing approaches taken to synthesize multiphase interleaving, each with tradeoffs in the ability to modulate duty-cycle when encountering a load, line, or setpoint transient, tradeoffs in the maximum number of interleaved phases supported, tradeoffs in the time necessary to refresh the phase delay from one active phase to the next active phase as phases are dynamically added and dropped, and tradeoffs in cost as expressed by silicon area required and power consumed corresponding to the multiphase interleaving collateral operating within an ‘controller’ integrated circuit.